Chapter 1: RISCs and MIPS 1.1 Pipelines 1.2 The MIPS Five-Stage Pipeline 1.3 RISC and CISC 1.4 Great MIPS Chips of the Past and Present 1.5 MIPS Compared with CISC Architectures Chapter 2: MIPS Architecture 2.1 A Flavor of MIPS Assembly Language 2.2 Registers 2.3 Integer Multiply Unit and Registers 2.4 Loading and Storing: Addressing Modes 2.5 Data Types in Memory and Registers 2.6 Synthesized Instructions in Assembly Language 2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions 2.8 Basic Address Space 2.9 Pipeline Visibility Chapter 3: Coprocessor 0: MIPS Processor Control 3.1 CPU Control Instructions 3.2 What Registers Are Relevant When? 3.3 CPU Control Registers and their encoding 3.4 CP0 Hazards?A Trap for the Unwary Chapter 4: How Caches work on MIPS 4.1 Caches and Cache Management 4.2 How Caches Work 4.3 Write-Through Caches in Early MIPS CPUs 4.4 Write-Back Caches in MIPS CPUs 4.5 Other Choices in Cache Design 4.6 Managing Caches 4.7 L2 and L3 caches 4.8 Cache Configurations for MIPS CPUs 4.9 Programming MIPS32/64 Caches 4.10 Cache Efficiency 4.11 Reorganizing Software to Influence Cache Efficiency 4.12 Cache Aliases Chapter 5: Exceptions, Interrupts, and Initialization 5.1 Precise Exceptions 5.2 When Exceptions Happen 5.3 Exception Vectors: Where Exception Handling Starts 5.4 Exception Handling: Basics 5.5 Returning from an Exception 5.6 Nesting Exceptions 5.7 An Exception Routine 5.8 Interrupts 5.9 Starting Up 5.10 Emulating Instructions Chapter 6: Low-level Memory Management and the TLB 6.1 The TLB/MMU hardware and what it does 6.2 TLB/MMU Registers Described 6.3 TLB/MMU Control Instructions 6.4 Programming the TLB 6.5 Hardware-friendly page tables and refill mechanism 6.6 Everyday Use of the MIPS TLB 6.7 Memory Management in a simpler OS Chapter 7: Floating-Point Support 7.1 A Basic Description of Floating Point 7.2 The IEEE754 Standard and Its Background 7.3 How IEEE Floating-Point Numbers Are Stored 7.4 MIPS Implementation of IEEE754 7.5 Floating-Point Registers 7.6 Floating-Point Exceptions/Interrupts 7.7 Floating-Point Control: The Control/Status Register 7.8 Floating-Point Implementation Register 7.9 Guide to FP Instructions 7.10 Paired-single floating-point instructions and MIPS 3D. 7.11 Instruction Timing Requirements 7.12 Instruction Timing for Speed 7.13 Initialization and Enabling on Demand 7.14 Floating-Point Emulation Chapter 8: Complete Guide to the MIPS Instruction Set 8.1 A Simple Example 8.2 Assembler Instructions and What They Mean 8.3 Floating-Point Instructions 8.4 Differences in MIPS32/64 Release 8.5 Peculiar Instructions and Their Purposes 8.6 Instruction Encodings 8.7 Instructions by Functional Group Chapter 9: Reading MIPS Assembler Language 9.1 A Simple Example 9.2 Syntax Overview 9.3 General Rules for Instructions 9.4 Addressing Modes 9.5 Object file and memory layout Chapter 10: Porting Software to MIPS 10.1 Low-level software for MIPS: A Checklist of Frequently Encountered Problems 10.2 Endianness: Words, Bytes, and Bit Order 10.3 Trouble With Visible Caches 10.4 Memory access ordering and re-ordering 10.5 Writing it in C Chapter 11: MIPS Software Standards (?ABI?s) 11.1 Data Representations and Alignment 11.2 Argument Passing and Stack Conventions for MIPS ?ABIs? Chapter 12: Debugging MIPS - debug and profiling features 12.1 The ?EJTAG? onchip debug unit 12.2 Pre-EJTAG debug support?break instruction and CP0 Watchpoints 12.3 PDTrace 12.4 Performance counters Chapter 13: GNU/Linux from Eight Miles High 13.1 Components 13.2 Layering in the kernel Chapter 14: How hardware and software work together 14.1 The life and times of an interrupt 14.2 Threads, critical regions and atomicity 14.3 What happens on a system call 384 14.4 How addresses get translated in Linux/MIPS Chapter 15: MIPS-specific issues in the Linux kernel 15.1 Explicit Cache Management 15.2 CP0 Pipeline hazards 15.3 Multiprocessor systems and coherent caches 15.4 Demon tweaks for a Critical Routine Chapter 16 Linux Application Code, PIC and Libraries 16.1 How link units get into a program 16.2 Global Offset Table (?GOT?) organization Appendix A: MIPS Multithreading A.1 What is MT A.2 Why is MT useful? A.3 How to do MT for a RISC architecture A.4 MT in action Appendix B: Other Optional extensions to the MIPS instruction set B.1 MIPS16 and MIPS16e B.2 The MIPS DSP ASE 440 B.3 MDMX MIPS Glossary Index
鄂公網(wǎng)安備 42010302001612號 