Foreword.
Preface
A knowledgments
Chapter 1 Fundamentals of Computer Design
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Ar hitecture
1.4 Trends in Technology
1.5 Trends in Power in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance and Price-Performance
1.11 Falla ies and Pitfalls
1.12 Con luding Remarks
1.13 Historical Perspectives and References Case Studies with Exercises by Diana Franklin
Chapter 2 Instru tion-Level Parallelism and Its Exploitation
2.1 Instruction-Level Parallelism: Concepts and Challenges
2.2 Basi CompilerTe hniques for Exposing lLP
2.3 Reducing Branch Costs with Prediction
2.4 Overcoming Data Hazards with Dynami Scheduling
2.5 Dynami Scheduling: Examples and the Algorithm
2.6 Hardware-Based Speculation
2.7 Exploiting lLP Using Multiple Issue and Stati Scheduling
2.8 Exploiting lLP Using Dynami Scheduling, Multiple Issue,and Speculation
2.9 Advanced Techniques for Instruction Delivery and Speculation
2.10 Putting It AIITogether:The Intel Pentium 4
2.11 Fallacies and Pitfalls
2.12 Concluding Remarks
2.13 Historical Perspective and References Case Studies with Exercises by Robert R Colwell
Chapter 3 Limits on Instruction-Level Parallelism
3.1 Introduction
3.2 Studies of the Limitations of lLP
3.3 Limitations On lLP for Realizable Processors
3.4 Crosscutting Issues: Hardwarecversus Software Speculation
3.5 Multithreading:Using lLP Support to Exploit Thread-Level Parallelism
3.6 Putting It All Together: Performance and Efficiency in Advanced Multiple-Issue Processors
3.7 Fallacies and Pitfalls
3.8 Concluding Remarks
3.9 Historical Perspective and References Case Study with Exercises by Wen-mei W. Hwu and John W. Sias
Chapter4 Multiprocessors and Thread-Level Parallelism
4.1 Introduction
4.2 Symmetri Shared-Memory Architectures
4.3 Performan eofSymmetri Shared-MemoryMultipro essors
4.4 Distributed Shared Memory and Dire tory-Based Coherence
4.5 Syn hronization:The Basi s
4.6 Models of Memory Consistency: An Introduction
4.7 Crossc utting Issues
4.8 Putting It All Together:The Sun T1 Multipro essor
4.9 Fallacies and Pitfalls
4.10 Concluding Remarks
4.11 Historical Perspective and ReferencesCase Studies with Exercises by David A. Wood
Chapter 5 Memory Hierar hy Design
5.1 Introduction
5.2 Eleven Advan ed Optimizations of Cache Performance
5.3 MemoryTechnology and Optimizations
5.4 Protection:Virtual Memory and Virtual Machines
5.5 Crosscutting Issues: The Design of Memory Hierarchies..
5.6 Putting It AlITogether:AMD Opteron Memory Hierarchy
5.7 Fallacies and Pitfalls
5.8 Con luding Remarks
5.9 Historical Perspective and References Case Studies with Exercises by Norman RJouppi
Chapter6 Storage Systems
6.1 Introduction
6.2 Advanced Topicscin Disk Storage
6.3 Definition and Examples of Real Faults and Failures
6.4 I/0 Performance, Reliability Measures, and Benchmarks
6.5 AcLittle Queuing Theory
6.6 Crosscutting Issues
6.7 Designing and Evaluating an I/0 System--The Internet Archive Cluster
6.8 Putting It All Together: NetApp FAS6000 Filer
6.9 Fallacies and Pitfalls
6.10 Concluding Remarks
6.11 Historical Perspective and References Case Studies with Exercises by Andrea C. Arpaci-Dusseau and Remzi H. Arpaci-Dusseau
Appendix A Pipelining: Basic and Intermediate Concepts
A.1 Introduction
A.2 The Major Hurdle of Pipelining--Pipeline Hazards
A.3 How Is Pipelining Implemented?
A.4 What Makes Pipelining Hard to Implement?
A.5 Extending the MIPS Pipeline to Handle Multicy lecOperations
A.6 Putting It AIITogether:The MIPS R4000 Pipeline
A.7 Crosscutting Issues
A.8 Fallacies and Pitfalls
A.9 Concluding Remarks
A.10 Historical Perspective and References
Appendix B Instruction Set Prindples and Examples
B.1 Introduction
B.2 Classifying Instruction Set Architectures
B.3 Memory Addressing
B.4 Type and Size of Operands
B.5 Operations in the Instruction Set
B.6 Instructions for Control Flow
B.7 Encoding an Instruction Set
B.8 Crosscutting Issues:The Role of Compilers
B.9 Putting It All Together:The MIPS Architecture
B.10 Fallacies and Pitfalls
B.11 Concluding Remarks
B.12 Historical Perspective and References
Appendix C Review of Memory Hierarchy
C.1 Introduction
C.2 Cache Performance
C.3 SixcBasi Cache Optimizations
C.4 Virtual Memory
C.5 Protection and Examples of Virtual Memory
C.6 Fallacies and Pitfalls
C.7 Concluding Remarks
C.8 Historical Perspective and References
Companion CD Appendices
Appendix D Embedded Systems
Updated by Thomas M. Conte
Appendix E Interconnection Networks
Revised by Timothy M Pinkston and Jose Duato
Appendix F Vector Processors
Revised by Krste Asanovi
Appendix G Hardware and Software for VL!W and EPIC
Appendix H Large-Scale Multiprocessors and Scientifi Applications
Appendix I Computer Arithmeti
by David Goldberg
Appendix J Survey of Instruction Set Architectures
Appendix K Historical Perspectives and References
Online Appendix (textbooks.celsevier, om/O 123 704901)
Appendix L Solutions to Case Study Exercises
Referen es
Index
鄂公網安備 42010302001612號 