邏輯設(shè)計基礎(chǔ)（第2版影印版）

Preface ix
Chapter 1 Introduction 1
Chapter 2 Switching Algebra and Logic Circuits 45
Chapter 3 The Karnaugh Map 129
Chapter 4 Function Minimization Algorithms 211
Chapter 5 Larger Combinational Systems 261
Chapter 6 Analysis of Sequential Systems 363
Chapter 7 The Design of Sequential Systems 409
Chapter 8 Solving Larger Sequential Problems 485
Chapter 9 Simplification of Sequential Circuits 533
Appendix A Laboratory Experiments 583
Appendix B Answers to Selected Exercises 612
Appendix C Chapter Test Answers 635
Index 647
v
CONTENTS
Preface ix
Chapter 1
Introduction 1
1.1
A Brief Review of Number Systems 3
1.1.1 Octal and Hexadecimal 6
1.1.2 Binary Addition 8
1.1.3 Signed Numbers 10
1.1.4 Binary Subtraction 13
1.1.5 Binary Coded Decimal （BCD） 15
1.1.6 Other Codes 16
1.2
The Design Process for Combinational
Systems 19
1.3
Don’t Care Conditions 22
1.4
The Development of Truth Tables 23
1.5
The Laboratory 27
1.6
Solved Problems 28
1.7
Exercises 37
1.8
Chapter 1 Test 42
Chapter 2
Switching Algebra and Logic
Circuits 45
2.1
Definition of Switching Algebra 46
2.2
Basic Properties of Switching
Algebra 49
2.3
Manipulation of Algebraic Functions 51
2.4
Implementation of Functions with AND， OR，
and NOT Gates 56
2.5
From the Truth Table to Algebraic
Expressions 61
2.6
Introduction to the Karnaugh Map 65
2.7
The Complement and Product of Sums 73
2.8
NAND， NOR， and Exclusive-OR
Gates 75
2.9
Simplification of Algebraic Expressions 82
2.10
Manipulation of Algebraic Functions and
NAND Gate Implementations 90
2.11
A More General Boolean Algebra 98
2.12
Solved Problems 100
2.13
Exercises 119
2.14
Chapter 2 Test 126
Chapter 3
The Karnaugh Map 129
3.1
Minimum Sum of Product Expressions Using
the Karnaugh Map 133
3.2
Don’t Cares 146
3.3
Product of Sums 150
3.4
Minimum Cost Gate Implementations 154
3.5
Five- and Six-Variable Maps 156
3.6
Multiple Output Problems 163
3.7
Solved Problems 174
3.8
Exercises 202
3.9
Chapter 3 Test 207
Chapter 4
Function Minimization
Algorithms 211
4.1
Quine-McCluskey Method for
One Output 211
4.2
Iterated Consensus for One Output 214
4.3
Prime Implicant Tables for One Output 218
4.4
Quine-McCluskey for Multiple Output
Problems 226
4.5
Iterated Consensus for Multiple Output
Problems 229
4.6
Prime Implicant Tables for Multiple Output
Problems 232
vi
4.7
Solved Problems 236
4.8
Exercises 257
4.9
Chapter 4 Test 258
Chapter 5
Larger Combinational
Systems 261
5.1
Delay in Combinational Logic Circuits 262
5.2
Adders and Other Arithmetic Circuits 264
5.2.1
Adders 264
5.2.2
Subtractors and Adder Subtractors 268
5.2.3
Comparators 269
5.3
Decoders 270
5.4
Encoders and Priority Encoders 276
5.5
Multiplexers 278
5.6
Three-State Gates 281
5.7
Gate Arrays—ROMs， PLAs， and PALs 282
5.7.1
Designing with Read-Only
Memories 287
5.7.2
Designing with Programmable Logic
Arrays 288
5.7.3
Designing with Programmable Array
Logic 291
5.8
Larger Examples 294
5.8.1
Seven-Segment Displays （First Major
Example） 295
5.8.2
An Error Coding System 302
5.9
Solved Problems 306
5.10
Exercises 346
5.11
Chapter 5 Test 358
Chapter 6
Analysis of Sequential
Systems 363
6.1
State Tables and Diagrams 365
6.2
Latches and Flip Flops 367
6.3
Analysis of Sequential Systems 376
6.4
Solved Problems 386
6.5
Exercises 399
6.6
Chapter 6 Test 407
Contents
vii
Chapter 7
The Design of Sequential
Systems 409
7.1
Flip Flop Design Techniques 414
7.2
The Design of Synchronous Counters 430
7.3
Design of Asynchronous Counters 440
7.4
Derivation of State Tables and State
Diagrams 443
7.5
Solved Problems 458
7.6
Exercises 475
7.7
Chapter 7 Test 483
Chapter 8
Solving Larger Sequential
Problems 485
8.1
Shift Registers 485
8.2
Counters 491
8.3
Programmable Logic Devices （PLDs） 498
8.4
Design Using ASM Diagrams 503
8.5
One-Shot Encoding 507
8.6
Hardware Design Languages 508
8.7
More Complex Examples 511
8.8
Solved Problems 517
8.9
Exercises 527
8.10
Chapter 8 Test 531
Chapter 9
Simplification of Sequential
Circuits 533
9.1
ATabular Method for State Reduction 535
9.2
Partitions 542
9.2.1
Properties of Partitions 545
9.2.2
Finding SP Partitions 546
9.3
State Reduction Using Partitions 549
9.4
Choosing a State Assignment 554
9.5
Solved Problems 560
9.6
Exercises 576
9.7
Chapter 9 Test 580

viii
Contents
Appendix A
Laboratory Experiments 583
A.1
Hardware Logic Lab 583
A.2
WinBreadboard. and
MacBreadboard. 587
A.3
Introduction to LogicWorks 4 589
A.4
Introduction to Altera Max+plusII 594
A.5
A Set of Logic Design Experiments 598
A.5.1
Experiments Based on Chapter 2
Material 598
A.5.2
Experiments Based on Chapter 5
Material 600
A.5.3
Experiments Based on Chapter 6
Material 603
A.5.4
Experiments Based on Chapter 7
Material 605
A.5.5
Experiments Based on Chapter 8
Material 606
A.6
Layout of Chips Referenced in the Text
and Experiments 607
Appendix B
Answers to Selected
Exercises 612
Appendix C
Chapter Test Answers 635
Index 647