1. ISA System Architectural Overview 2. PCI and PCI-X System Architectural Overview 3. Generic PCI Hardware Operation 4. Functional Interaction between PCI and PCLX Resources 5. Signal Line Definition 6. Detailed Bus Transaction Operation 7. Bridge and Interface Protocol 8. Master and Target Termination 9. Bus Segment Ownership 10. Parity and Bus Errors 11. Reset, Power, and Signal Line Initialization 12. Signal Line Timing and Electrical Requirements 13. Connector, Platform, and Add-In Card Design 14. Latency and Performance 15. Mechanical Specification 16. System Resources 17. PCI Configuration Address Space 18. PCI Header Type 00H 19. PCI Header Type 01H 20. PCI Bridges 21. Overview of System BIOS 22. PCI System BIOS Software Interface 23. PCI Device Configuration 24. PCI Capabilities Appendix A. PCI Class Code Register Encoding Appendix B. User Definable Configuration Items Appendix C. VGA Palette Snooping Appendix D. ISA Aliasing Appendix E. PCI and ISA Aliasing Appendix F. Common Problems to Avoid Appendix G. IRQ Routing Table Example Index