計(jì)算機(jī)體系結(jié)構(gòu)習(xí)題與解答（英文版）

CHAPTER 1 Introd uction

1.1 Purpose of This Book
1.2 Background Assumed
1.3 Material Covered
1.4 Chapter Objectives
1.5 Technological Trends
1.6 Measuring Performance
1.7 Speedup
1.8 Amdahl's Law
1.9 S
Solved Problems

CHAPTER 2 Data Representations and Computer Arithmetic

2.1 Objectives
2.2 From Electrons to Bits
2.3 Binary Representation of Positive Integers
2.4 Arithmetic Operations on Positive Integers
2.5 Negative Integers
2.6 Floating-Point Numbers
2.7 S
Solved Problems

CHAPTER 3 Computer Organization

3.1 Objectives
3.2 Introduction
3.3 Programs
3.4 Operating Systems
3.5 Computer Oganization
3.6 Summary
Solved Problems

CHAPTER 4 Programming Models

4.1 Objectives
4.2 Introduction
4.3 Types of Instructions
4.4 Stack-Based Architectures
4.5 General-Purpose Register Architectures
4.6 Comparing Stack-Based and General-Purpose Register
Architectures
4.7 Using Stacks to Implement Procedure Calls
4.8 Summary '
Solved Problems

CHAPTER 5 Processor Design

5.1 Objectives
5.2 Introduction
5.3 Instruction Set Architecture
5.4 Processor Microarchitecture
5.5 S
Solved Problems

CHAPTER 6 Pipelining

6.1 Objectives
6.2 Introduction
6.3 Pipelining
6.4 Instruction Hazards and Their Impact on Throughput
6.5 Predicting Execution Time in Pipelined Processors
6.6 Result Forwarding (Bypassing)
6.7 S
Solved Problems

CHAPTER 7 Instruction-Level Parallelism

7.1 Objectives
7.2 Introduction.
7.3 What is Instruction-Level Parallelism?
7.4 Limitations of instruction-Level Parallelism
7.5 Superscalar Processors
7.6 In-Order versus Out-of-Order Execution
7.7 Register Renaming '
7.8 VLIW Processors
7.9 Compilation Techniques for Instruction-Level Palallelism
7.1O S
Solved Problems

CHAPTER 8 Memory Systems

8.1 Objectives
8.2 Introduction
8.3 Latency, Throughput and Bandwidth
8.4 Memory Hierarchies
8.5 Memory Technologies
8.6 S
Solved Problems

CHAPTER 9 Caches

9.1 Objectives
9.2 Introduction
9.3 Data Caches, Instruction Caches, and Unified Caches
9.4 Describing Caches
9.5 Capacity
9.6 Line Length
9.7 Associativity
9.8 Replacement Policy
9.9 Write-Back versus Write-Through Caches
9.1O Cache Implementations
9.11 Tag Arrays
9.12 Hit/Miss Logic
9.13 Data Arrays
9.14 Categorizing Cache Misses
9.15 Multilevel Caches
9.16 S
Solved Problems

CHAPTER IO Virtual Nemory

l0.1 Objectives '
10.2 Introduction
10.3 Address Translation
10.4 Demand Paging versus Swapping
10.5 Page Tables
10.6 Translation Lookaside Buffers
10.7 Proteaion
10.8 Caches and Virtual Memory
10.9 Summary
Solved Problems

CHAPTER 11 I/O

11.1 Objectives
11.2 Introduction
11.3 I/0 Buses
11.4 Interrupts
11.5 Memory-Mapped I/O
11.6 Direct Memory Aceess
11.7 I/O Devices
11.8 Disk Systems
11.9 S
Solved Problems

CHAPTER 12 Multiprocessors

12.1 Objectives
12.2 Introduction
12.3 Speedup and Performance
12.4 Multiprocessor Systems
12.5 Message-Passing Systems
12.6 Shared-Memory Systems
12.7 Comparing Message-Passing and Shared Memory
12.8 Summary
Solved Problems

INDEX