ListofFigures
ForewordbyClaytonChristensen
ForewordbyJohnHennessy
Author'sPreface
Acknowledgments
ChapterITheCaseforaNewSOCDesignMethodology
1.1TheAgeofMegagateSOCs
1.1.1Moore'sLawMeansOpportunityandCrisis
1.1.2Roadblock1:BuildingtheWrongChip
1.1.3Roadblock2:BuildingtheChipWrong
1.2TheFundamentalTrendsofSOCDesign
1.2.1ANewSOCforEverySystemisaBadIdea
1.2.2SOCDesignReform:LowerDesignCostandGreaterDesignFlexibility
1.2.3Concurrency
1.2.4Programmability
1.2.5ProgrammabilityVersusEfficiency
1.2.6TheKeytoSOCDesignSuccess:Domain-SpecificFlexibility
1.3What'sWrongwithToday'sApproachtoSOCDesign?.
1.3.1What'sWrongwithTraditionalProcessors?
1.3.2What'sWrongwithTraditionalSOCMethodology?
1.4Preview:AnImprovedDesignMethodologyforSOCDesign
1.4.1TheSOCDesignFlow
1.4.2ConfigurableProcessorasBuildingBlock
1.4.3ATrivialExample
1.4.4ResultsofApplication-SpecificProcessorConfiguration
1.4.5TheProcessorasSOCBuildingBlock
1.4.6SolvingtheSystemDesignProblem
1.4.7ImplicationsofImprovedSOCMethodology
1.4.8TheTransitiontoProcessor-basedSOCDesign
1.5FurtherReading
Chapter2SOCDesignToday
2.1HardwareSystemStructure
2.1.1HowIsRTLUsedToday?
2.1.2Control,DataPath,andMemory
2.1.3HardwareTrends
2.2SoftwareStructure
2.2.1SoftwareTrends
2.3CurrentSOCDesignFlow
2.4TheImpactofSemiconductorEconomics
2.5SixMajorIssuesinSOCDesign
2.5.1ChangingMarketNeeds
2.5.2InadequateProductVolumeandLongevity
2.5.3InflexibilityintheSemiconductorSupplyChain
2.5.4InadequatePerformance,Efficiency,andCost
2.5.5Risk,Cost,andDelayinDesignandVerification
2.5.6InadequateCoordinationBetweenHardwareandSoftwareTeams
2.5.7SolvingtheSixProblems
2.6FurtherReading
Chapter3ANewLookatSOCDesign
3.1.1TheBasicsofProcessor-CentricSOCArchitecture
3.1.2ProcessorGeneration
3.2AcceleratingProcessorsforTraditionalSoftwareTasks
3.2.1TheEvolutionofGenericProcessors
3.2.2ExplainingConfigurabilityandExtensibility
3.2.3ProcessorExtensibility
3.2.4Designer-DefinedInstructionSets
3.2.5MemorySystemsandConfigurability
3.2.6TheOriginsofConfigurableProcessors
3.3Example:TensilicaXtensaProcessorsforEEMBCBenchmark
3.3.1EEMBCConsumerBenchmarks
3.3.2Telecommunications
3.3.3EEMBCNetworkingBenchmarks
3.3.4TheProcessorasRTLAlternative
3.4SystemDesignwithMultipleProcessors
3.4.1AvailableConcurrency
3.4.2ParallelismandPower
3.4.3APragmaticViewofMultipleProcessorDesignMethodology
3.4.4FormsofPartitioning
3.4.5ProcessorInterfaceandInterconnect
3.4.6CommunicationsbetweenTasks
3.5NewEssentialsofSOCDesignMethodology
3.5.1SOCDesignFlow
3.5.2TheEssentialPhasesoftheNewFlow
3.6AddressingtheSixProblems
3.6.1MaketheSOCMoreProgrammable
3.6.2BuildanOptimizedPlatformtoAggregateVolume
3.6.3UsePortableIPFoundationsforSupplyLeverage
3.6.4OptimizeProcessorsforPerformanceandEfficiency
3.6.5ReplaceHard-wiredDesignwithTunedProcessors
3.6.6UnifyHardwareandSoftwarewithProcessor-CentricSOCMethodology
3.6.7ComplexSOCandtheSixProblems
3.7FurtherReading
Chapter4System-LevelDesignofComplexSOCs
4.1ComplexSOCSystemArchitectureOpportunities
4.1.1TheBasicProcessofParallelDesign
4.1.2TheSOCasaNetworkofInteractingComponents
4.1.3ImpactofSiliconScalingonSystemPartitioning
4.1.4WhyMultipleProcessors
4.1.5TypesofConcurrencyandSystemArchitecture
4.1.6Latency,BandwidthandCommunicationsStructure
4.1.7ReliabilityandScalabilityinSOCCommunicationsArchitecture
4.1.8CommunicationsProgrammingFlexibility
4.1.9Earlyvs.Late-BindingofInteractionMechanisms
4.2MajorDecisionsinProcessor-CentricSOCOrganization
4.2.1TheStartingPoint:EssentialInterfacesandComputation
4.2.2ParallelizingaTask
4.2.3AssigningTaskstoProcessors
4.2.4ChoosingtheRightCommunicationsStructure
4.3CommunicationDesign=SoftwareMode+Hardware
Interconnect
4.3.1SoftwareCommunicationModes
4.3.2MessagePassing
4.3.3SharedMemory
4.3.4DeviceDriver
4.4HardwareInterconnectMechanisms
4.4.1Buses
4.4.2DirectConnectPorts
4.4.3DataQueues
4.4.4Time-MultiplexedProcessor
4.5Pefformance-DrvenCommunicationDesign
4.5.2SystemModelingLanguages
4.5.3SystemModelingExample:XTMP
4.5.4BalancingComputationandCommunications
4.6TheSOCDesignFlow
4.6.1RecommendedDesignFlow
4.6.2ShiftsinSOCDesignMethodology
4.7Non-ProcessorBuildingBlocksinComplexSOC
4.7.1Memories
4.7.2I/OPeripherals
4.7.3HardwiredLogicBlocks
4.8ImplicationsofProcessor-CentricSOCArchitecture
4.9FurtherReading
Chapter5ConfigurableProcessors:ASoftwareView
5.1ProcessorHardware/SoftwareCogeneration
5.1.1Applications,ProgrammingLanguages,andProcessorArchitecture
5.1.2AQuickExample:PixelBlending
5.2TheProcessofInstructionDefinitionandApplicationTuning
5.2.1ProfilingandPerformance
5.2.2NewInstructionsforPerformanceandEfficiency
5.3TheBasicsofInstructionExtension
5.3.1InstructionExtensionMethods
5.3.2UpgradingtheApplication
5.3.3TheTradeoffbetweenInstruction-SetPerformanceandGenerality
5.3.4OperationFusion
5.3.5CompoundOperations
5.3.6SIMDInstructions
5.4TheProgrammer'sModel
5.4.1TheBaseUserInstructionSet
5.4.2TheApplication-SpecificInstructionSet
5.4.3TheSystem-ProgrammingInstructionSet
5.5ProcessorPerformanceFactors
5.5.1TheSoftwareDevelopmentEnvironment
5.5.2TheSoftwareRuntimeEnvironment
5.5.3ProcessorGenerationFlow
5.6Example:TuningaLargeTask
5.7Memory-SystemTuning
5.7.1BasicMemory-SystemStrategy
5.7.2DetailedMemory-SystemTuning
5.7.3AggregateMemorySystemPerformance
5.7.4Inner-LoopData-ReferenceTuning
5.8LongInstructionWords
5.8.1CodeSizeandLongInstructions
5.8.2LongInstructionWordsandAutomaticProcessorGeneration
5.9FullyAutomaticInstruction-SetExtension
5.10FurtherReading
Chapter6ConfigurableProcessors:AHardwareView
6.1ApplicationAcceleration:ACommonProblem
6.2IntroductiontoPipelinesandProcessors
6.2.1PipeliningFundamentals
6.2.2RISCPipelineBasics
6.2.3PipelinesforExtendedInstruction-SetImplementation
6.2.4GuaranteeofCorrectnessinProcessorHardwareExtension
6.3HardwareBlockstoProcessors
6.3.1TheBasicTransformationofHardwareintoInstructions
6.3.2OnePrimitiveOperationperInstruction
6.3.3MultipleIndependentOperationsperInstruction
6.3.4PipelinedInstruction
6.3.5TradeoffsinMappingHardwareFunctionstoProcessorInstructions
6.4MovingfromHardwiredEnginestoProcessors
6.4.1TranslatingFinite-StateMachinestoSoftware
6.4.2DesigningApplication-SpecificProcessorsforFlexibility
6.4.3MovingfromMicrocodedEnginestoProcessors
6.4.4MicrocodeDataPaths
6.4.5EncodingOperations
6.4.6Microprograms
6.5DesigningtheProcessorInterface
6.5.1Memory-MappedRAM
6.5.2Memory-MappedQueuesandRegisters
6.5.3Wire-BasedInputandOutput
6.6AShortExample:ATMPacketSegmentationandReassembly
6.7NovelRolesforProcessorsinHardwareReplacement
6.7.1TheDeeplyBuffedTaskEngine
6.7.2DesigningwithSpareProcessors
6.7.3TheSystem-MonitorProcessor
6.8Processors,HardwareImplementation,andVerificationFlow
6.8.1HardwareFlow
6.8.2VerificationFlow
6.9ProgressinHardwareAbstraction
6.10FurtherReading
Chapter7AdvancedTopicsinSOCDesign
7.1PipeliningforProcessorPerformance
7.2InsideProcessorPipelineStalls
7.2.2PipelinesandExceptions
7.2.3AlternativePipeliningforComplexInstructions
7.3OptimizingProcessorstoMatchHardware
7.3.1OvercomingDifferencesinBranchArchitecture
7.3.2OvercomingLimitationsinMemoryAccess
7.4MultipleProcessorDebugandTrace
7.4.1MPDebug
7.4.2MPTrace
7.5IssuesinMemorySystems
7.5.1PipeliningwithMultipleMemoryPorts
7.5.2MemoryAlignmentinSIMDInstructionSets
7.5.3SynchronizationMechanismsforSharedMemory
7.5.4InstructionROM
7.6OptimizingPowerDissipationinExtensibleProcessors
7.6.1CorePower
7.6.2ImpactofExtensibilityonPerformance
7.6.3MemoryPower
7.6.4CachePowerDissipationGuide
7.7EssentialsofTIE
7.7.1TIEOperations
7.7.2TIEStatesandRegisterFiles
7.7.3ExternalTIEPortsandQueues
7.7.4TIEConstants
7.7.5TIEFunctionScheduling(useanddel)
7.7.6UsingBuilt-inRegisters,Interfaces,andFunctionswithTIE
7.7.7SharedandIterativeTIEFunctions
7.7.8Multi-SlotInstructions
7.8FurtherReading
Chapter8TheFutureofSOCDesign:TheSeaofProcessors
8.1.1What'sHappeningtoSOCDesign?
8.1.2SOCandROI
8.1.3TheDesigner'sDilemma
8.1.4TheLimitationsofGeneral-PurposeProcessors
8.1.5TheNewProcessor
8.1.6WhatMakesTheseProcessorsDifferent?
8.1.7TheSOCDesignTransition
8.2WhyIsSoftwareProgrammabilitySoCentral?
8.3LookingintotheFutureofSOC
8.4ProcessorScalingModel
8.4.1SummaryofModelAssumptions
8.5FutureApplicationsofComplexSOCs
8.6TheFutureoftheComplexSOCDesignProcess
8.7TheFutureoftheIndustry
8.8TheDisruptive-TechnologyView
8.9TheLongView
8.10FurtherReading
Index
鄂公網(wǎng)安備 42010302001612號(hào) 