Introduction Acknowledgments Open Letter to Circult Designers Chapter 1 Digital Layout Chapter Preview Opening Thoughts on Digital Layout Design Proces Verifying the Circuitry Logic Compiling a Netlist Drive Strength Clock Tree Synthesis Layout Process Floorplanning Block Placement Gate Grouping Block Level Connectivity Using Flylines Timing Checks Placement I/O Drivers Routing Power Nets Strapping Clock Net Wiring Other Critical Nets Remaining Nets Finishing the Wiring by Hand Prefabricated Gate Array Chips Verification Design Verification Physical Verification GDSII File DRC and LVS Checks Library Management Summary and Flowchart Colsure on Digital Layout Here's What We've Learned Chapter 2 Standard Cell Techniques Chapter Preview Opening Thoughts on Standard Cell Techniques Standardized Grids Grid-Based Systems Determining Grid Size Rule-Based Routers Directional Layer Technique Library Rules for Grid-Based Systems Input and Output Alignment Fixed Height,Variable Width Determining Wire Garge Common N Well Half-Grid Cell Sizing Half Design Rule Routing Channels Antenna Rules Standardized Input and Output Cells Using Standardization in Analog Mask Design Closure on Standard Cell Techniques Here's What We've Learned Chapter 3 Analog Layout Chapter Preview Opening Thoughts on Analog Layout Digital Skills vs.Analog Skills Difference of Scale Difference of Teamwork Difference of Completion Schedule Difference of Innovation Difference of Constraints Difference of Understanding Circuit Techniques Three Key Questions QUESTION 1:What does this circuit do? QUESTION 2:How much current does it take? Calculating Crrent Densities QUESTION 2a:Where are the high and low current paths? Device Orientation QUESTION 3:What matching requirements are there? Additional Questions Bipolar Analog Expctations of an Analog Mask Designer Closure on Analog Layout Here's What We've Learned Appendix:Key Questions Discussion Chapter 4 Parasitics Chapter Preview Opening Thoughts on Parastics Parasitic Capacitance Wire Length Metal Selection Metal over Metal Parasitic Resistance Calculating IR Drops Wiring Options Parasitic Inductance Device Parasitics CMOS Transistor Example Bipolar Transistor Example Full Custom Options Closure on Parasitics Here's What We've Learned Chapter 5 Matching Chapter Preview Opening Thoughts on Parasitics Parasitic Capacitance Wire Length Metal Selection Metal over Metal Parsitic Resistance Calculating IR Drops Wiring Options Parsitic Inductance Device Parsitics CMOS Transistor Example Bipolar Transistor Example Full Custom Options Closure on Parasitics Here's What We've Learned Chapter 5 Matching Chapter Preview Opening Thoughts on Matching Importance of Layout Importance of Communication Simple Matching Root Device Method Imterdigitaing Devices Dummy Devices Common Centroid Cross-Quading Symmetry Matching Signal Paths Device Size Choices Closure on Matching Here's What We've Learned Rules of Matching Chapter 6 Noise Issues Chapter Preview Opening Thoughts on Noise Issues Noisy Neighbors CommonSense Noise Solutions Turn Down the Volume Rock Band Moves Inside Their House Go Inside Your Own House Close All Windows Call the Sheriff Move to a New Neighborhood Wire Solutions Coaxial Shielding Differential Signals Decoupled Power Rails Stacked Power Rails Harmonic Interference Closure on Noise Issues Here's What We've Learned Chapter 7 Floorplanning Chapter Preview Opening Thoughts on Floorplanning Primary Drivers of Floorplanning Pin-Driven Planning Effect of Pin Placement ESD Supply Strategies Block-Driven Planning Signal-Diven Planning Reshaping Blocks Sizing Estimates Leaving Enough Room Estimating with Existing Circuitry Closeure on Floorplanning Here's What We've Learned Chapter 8 General Techniques Chapter Preview General Techniques #1 Pick Five or Six Non-minimum Design Rules #2 Get Thee to the Lowest Parasitic Metal #3 Plenty of Wide Wiring and Vias #4 Don't Believe Your Circuit Designer #5 Use a Consistent Orientation #6 Don't Believe Your Circuit Designer #7 Keep Off the Blocks #8 Care for Your Sensitive and Noisy Signals Early #9 If It Looks Nice,It Will Work #10 Learn Your Process #11 Don't Let Noise Find the Substrate #12 Spresd Your Spinach around Your Dinner Plate #13 Copy and Raname Cells before Making Changes #14Remember Your Hierarchy Level #15 Build-in Easy Metal Revisions #16 Draw Big Power Buses #17 Break Up Large Circuits Closure on General Techniques Ancient Senrets of Mask Design Chapter 9 Packaging Chapter Preview Opening Thoughts on Packaging Bonding Methods Ultrasonic Wedge Bonding Ultrasonic Ball Bonding Flip Chip Technology Multi-Tier Packaging Issues in Packaging Overall Appearance 45-Degree Rule Minimal Silicon Overlap Wire Length Pad Distribution Sizing Estimates Pad-Limited Design Core-Limited Design Padkage Maximum Check Final Die Size Calculations Filling Pad Gaps Closure on Packaging Here's What We've Learned Chapter 10 Verification Chapter Preview Opening Thoughts on Verification Checking Software Design Rule Check(DRC) Boolean Command Lines AND Function OR Function NOT Function Rule Checking Command Lines Layout Versus Schematic(LVS) Netlists Problem Solving 1.Check Number of Devices 2.Check Types of Devices 3.Check Number of Nets 4.Soluing Complex Net Problems a.Power Supplies 5.Don't Trust Your Circuit Designer 6.Check for Possible Swapping Over 7.Check for a Top Level Short 8.Check for Ninja Invisibility 9.Know Your Circuits 10.Let Others Help Closure on Verification Here's What We've Learned Chapter 11 Data Formats Chapter Preview Opening Thoughts on Data Formats Industry Standard Database Formats Header Information Coordinating Resolutions Pattern Generation Know Your Grids Closure on Data Formats Here's What We've Learned Chapter Study #1 CMOS Amplifier The New Job Assignment Bill Reasons His Floorplan Bill Thinks Through His Layout Ted Returns Bill Rethinks The Chip Is Assembled Packaging Appendix Case Study #2 Bipolar Mixer Introduction to Case Study 2 The Assignment "What Does the Circuit Do?" "What Are the Circuit Requirements?" Bipolar Trasistor Review First Layout Initial Overview Current Source Transistors Resistors Lower Pair Emitters Bases Collectors Upper Quad Emitters Bases Collectors Loads Output Resistors Analysis of First Layout Bipolar Transistor Layout-Wrap-Around Technique Second Layout Current Source Emitters Bases Collectors Resistors Lower Pair Interdigitation Plan Emitters Collectors Bases Inputs Upper Quad Interdigitation Plan Emitters Collectors Bases Inputs Loads Interdigitation Plan Resistors Outputs Analysis of Second Layout Third Layout Lower Pair Cross-Quading Plan Emitters Collectors Bases Inputs Final Analysis Comparison of Case Study 1 and Case Study 2 Beginnings The Four Engineers Outtakes Contact Us Suggested Readings and Resources Educational Programs Glossary Index
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